Verisity and HCL Technologies Deliver ARM e Verification Component

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 9, 2002--Verisity Ltd. (Nasdaq:VRST), the leader in functional verification automation, and its Verification Alliance(TM) partner HCL Technologies, today announced the availability of an e Verification Component (eVC(TM)) for the ARM7 ISA standard. eVCs are reusable plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. HCL Technologies' new ARM eVC contains critical verification capabilities for the ARM v4T ISA, drastically cutting verification environment development time. The ARM v4T ISA eVC is expected to meet full e Reuse Methodology (eRM(TM)) compliance in Q402, thereby interoperating seamlessly with all other eRM compliant eVCs (see related release, "Verisity Announces e Reuse Methodology," dated September 9, 2002).

"Our expertise in microprocessor design, in addition to Verisity's Specman Elite(TM) functional verification methodology, resulted in creation of the ARM v4T ISA eVC," said Ashok Madaan, GPM, ASIC team, HCL Technologies Noida. "We are looking forward to leveraging the process of developing eVCs for upcoming microprocessors and bus standards to further help our customers reduce the overall verification investment. We are already working on a PCI Express eVC, which is scheduled to be released in Q402. This reflects our confidence and commitment in eVC design methodology."

By utilizing eVCs, verification engineers can reduce the amount of work needed to create a verification environment and shorten the time it takes to begin running self-checking tests. The ARM eVC can be used in a variety of design applications and includes integrated components: input generator, dedicated assembler and injector, reference ARM v4T ISA model, checker and functional coverage elements.

"It is clear that eVCs offer our customers an unparallel solution to their most difficult verification challenges, said Dave Tokic, director of strategic marketing for Verisity. "HCL Technologies is a key Verification Alliance partner making significant strides in the verification reuse movement."

About ARM v4T ISA eVC

The ARM v4T ISA eVC can be utilized to verify a stand-alone DUT targeting the ARM v4T ISA or used to verify a SoC environment targeted around an ARM core. Once eRM compliant, the ARM v4T ISA eVC will meet the standard requirements for full interoperability with all other eVCs developed using Verisity's e Reuse Methodology -- a comprehensive guideline for eVC development best practices.

ARM v4T ISA eVC supports both 32-bit and Thumb instructions with both directed and random test vector generation. It has built-in coverage analysis for generated ISA conditions and is supplied with ARM v4T ISA compliant test vectors.

e Verification Components

Each eVC includes three integrated components: a stimuli generator for injecting and generating traffic, monitors and checkers for viewing outputs and checking protocol rules, and coverage reports showing the functional coverage of scenarios. They can be used in a variety of design applications and are available for a wide array of industry standards.

eVCs foster verification reuse because they can easily be moved from module-level verification to SoC-level verification, as well as from one chip design to another. Users can drop them into their designs and drastically cut the time it takes to create a verification environment.

For a complete listing of eVCs available, please visit http://www.verisity.com and customers can log in to https://www.verificationvault.com.

e Reuse Methodology (eRM)

eRM provides dramatic functional verification productivity gains, most notably for advanced ASICs, SoCs and processors. eRM is a complete reuse methodology that codifies the best practices for eVC development. eRM delivers a common eVC usage model, and ensures that all eRM compliant eVCs will interoperate seamlessly regardless of origin. In addition, new eRM technology in Specman Elite(TM), Verisity's flagship testbench automation tool, increases the power of eRM compliant eVCs to generate and synchronize complex multi-transaction scenarios.

Pricing and Availability

The ARM eVC is available now from HCL Technologies. For pricing, contact HCL Technologies at ashok@noida.hcltech.com.

About HCL Technologies

HCL Technologies provides technology solutions in the areas of embedded systems, ASIC design and verification, networking and telecom. Services provided include high-end SoC design, ASIC design, ASIC/SoC verification, ASIC physical design, high-speed board and FPGA design, embedded software and complete system design. HCL Technologies is headquartered in Sunnyvale, USA and has 13 development centers in India. To learn more, visit http://www.hcltechnologies.com

About Verisity

Verisity is the leading provider of proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to the communications and other high growth segments of the electronics industry. The Company's products automate the process of detecting flaws in these designs, enabling customers to deliver higher quality products, accelerate time-to-market and reduce overall product development costs.

Verisity Design, Inc.'s principal executive offices are located in Mountain View, Calif. The Company's principal research and development offices are located in Rosh Ha'ain, Israel. For more information, see Verisity's web site at http://www.verisity.com.

Verisity is a registered trademark of Verisity Design, Inc. eVCs, Specman Elite and Verification Alliance are trademarks of Verisity Design, Inc. All other trademarks are the property of the respected owners and should be treated as such.

     Verisity Design, Inc.
     Ric Chope, 650/934-6820
     rchope@verisity.com